This invention relates to a data transfer apparatus, more particularly a data transfer apparatus in which, in a memory device utilizing a plurality of bytes as a unit of an input or output, a portion of the memory region in which a unit of data to be transferred is stored overlaps a portion of the memory region to which the unit of data is to be transferred.
Generally an information processing apparatus is constituted by such basic elements as a central processing unit (CPU), a memory device storing a program, data, etc., and input and output (I/0) devices. This CPU comprises an instruction processing unit which functions to process instructions, operands, and addresses and an arithmetic operation unit. The former makes an access to the memory device and the arithmetic operation unit causes the same to perform desired arithmetic operations in response to an instruction obtained from the memory device and then designates an address of the memory device, in accordance with the result of the arithmetic operation, to write the operated and processed data into the memory device.
FIG. 1 shows the essential portions of a central processing unit (CPU) operatively connected to a prior art data transfer apparatus comprising, as essential component elements, a memory device 11 and a CPU 12. The CPU performs instruction processing, operand processing and address processing. The CPU comprises an instruction processing unit 12A connected to receive instructions from the memory device 11, and an arithmetic operation processing unit 12B which performs necessary arithmetic operations based on the instructions from the instruction processing unit 12A. The instruction processig unit 12A shown in the drawing comprises a first memory address register which stores the address of a byte in memory device 11 which address is the beginning or origination address of a plurality of bytes to be transferred to the destination or receive byte address of a second plurality of bytes, which destination or receive byte address is stored in a second memory address register. The first memory address register will hereinafter be referred to as transfer origination side address register 13 and the second memory address register will hereinafter be referred to as transfer receiving side address register 14. The transfer origination side address register 13 and the transfer receiving side address register 14 are capable of incrementing by 1. The instruction processing unit 12a further comprises a word address coincidence detecting circuit 15 which compares the word addresses of both registers 13 and 14 so as to detect whether these addresses coincide with each other or not, a control circuit 16 for reading from memory device 11 in accordance with the two least significant bits of the transfer originating side address registor 13 and the output of the detecting circuit 15, and a control circuit 17 for writing to memory device 11 in accordance with the least significant two bits of the transfer receiving side address register 14.
The arithmetic operation processing unit 12B comprises a renewal control circuit 18 which renews first memory data register hereinafter referred to as transfer originating side data register 19 with the data in the transfer originating side address register 13 in response to the output of the word address coincidence detecting circuit 15. The transfer originating side data register 19 holds the data words to be transferred to the memory device 11 (although in the following description one word comprises four bytes the number of bytes may be variable). A selection circuit 20 selects one byte of the data register 19 represented by the least significant two bits (a byte address in a word) of the transfer originating side address register 13 and a second memory data register hereinafter referred to as transfer receiving side data register 21 which holds one byte from the selecting circuit 20 in a byte position represented by the least significant two bits transfer receiving side address register 14.
The operation of the apparatus shown in FIG. 1 will now be described with reference to FIGS. 2A through 2F. FIG. 2A shows an arrangement of the data in the memory device 11 before transfer, that is the transfer originating side data arrangement, and 8 byte data A-H is transferred from an address a.sub.1 to an address a.sub.2. Dual lines between groups of 4 bytes represent paired bytes which are handled as a single unit or an information, and .circle.P and .circle.R represent words.
FIG. 2B shows the transfer operation in which the data word .circle.P in the memory device 11 is transfer originating side data register 19. Then the data to be transferred is stored (in this example, the data A in the second address of transfer originating side data register 19) in a position previously designated by the transfer receiving side address register 14. The data stored in the transfer receiving side data register 21 is transferred to a predetermined byte (the fourth address) of the transfer receiving side data word .circle.P of the memory device 11.
FIG. 2C shows the operation in which after the remaining two bytes (the third and fourth addresses) of the transfer originating side data word .circle.P has been transferred to the receiving side data register 21, and in view of the fact that the transferred data word .circle.Q is coincident with the received data word, a portion of the data in the receiving side data register 21 including the transferred byte is stored in the transfer originating side data word .circle.Q and then the transfer originating side data word .circle.Q is read and stored in the transfer originating side data register 19.
FIG. 2D is a diagram showing that, subsequent to the operation shown in FIG. 2C the operation as that shown in FIG. 2B is performed. FIG. 2E shows an operation similar to that shown in FIG. 2B, while FIG. 2F shows the content of the memory device 11 at a time when the transfer of 8 bytes has been completed.
As can be noted from the foregoing description regarding the operation of the prior art apparatus, in order to process one word it is necessary to access the memory device three times including a read out operation of the transfer originating data, a writing operation thereof, and a writing operation of the transferred data.